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Feedback/bias return connection on LNK6663K

Posted by: marcj on

In the datasheet for the LNK6663K, there are are two statements that I find conflicting. On page 3, the description for the source pin says:

SOURCE (S) Pin:
This pin is the power MOSFET source connection. It is also the ground reference for the BYPASS, FEEDBACK, PROGRAM and COMPENSATION pins.

This is clear to me, as the feedback voltage would be measured by the device between its Feedback and Source pins. There should not be any noise source in series with the feedback loop.

However, on pages 10-12, it is recommended to connect the bias winding return to the negative pin of the bulk capacitor. While star grounds used to be all the rage in the 1980s, I prefer to understand the actual current loops in my design. I'm adding a copy of Figure 15 here.

  • In light green, I indicated the current path that closes the primary loop (bulk capacitor, primary winding, drain, source, back to bulk cap). Any voltage drop here will be added to the feedback voltage. Surely that can't be right?
  • In dark green is the loop that the ground return path takes. Any voltage induced here by magnetic fields will be added to the feedback voltage. A ground plane could help in multilayer designs.
  • In purple, I show the shortest path that closes the loop for the feedback voltage. Nature, by itself, will use the loop with the minimum possible area, which would be to pin 12. That's exactly where you need it.

With the roundabout trace suggested in Figure 15, the feedback loop current is forced to take an unnatural path that adds noise/offset to the signal. Could you please explain how that would be better than a direct connection to source?

Thanks!

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Comments

Submitted by PI-Chloe on 05/05/2024

Hi Marcj,  

Good day! 

Thanks for your question. 

The supply pin (BP) and control circuit pin (CP, FB,  PD)  should have close connection to the IC Source. 

For the Bias Supply grounding, it is start connected to the Bulk Cap.  This was implemented to mitigate any potential concern during ESD and Common Mode Surge. 

ESD and common mode surges can pass thru the bias winding via parasitic capacitances of the bias winding and secondary winding. 

If this happen, it will contaminate the ground of the control and supply pin of the IC that can cause IC to misbehave.

 When bias ground is connected to the Bulk cap, It will not be easy to ESD and common surge energy to contaminate the bias ground. 

Thanks 

Regards 

PI-Chloe

Submitted by PI-Chloe on 05/08/2024

Hi Marcj,  

Good Day

Additional on your comment: 

"In light green, I indicated the current path that closes the primary loop (bulk capacitor, primary winding, drain, source, back to bulk cap). Any voltage drop here will be added to the feedback voltage. Surely that can't be right?"

 

          - Feedback sensing happens during OFF time of the FET. 

          - Meaning, there will be no current flowing from IC SOURCE Eto Bulk Cap when the Feedback is being sense.  We can expect that there will be additional voltage drop during feedback sensing of the IC. 

 

Thanks 

Regards 

Patrick